Melnikoff, Stephen Jonathan and Quigley, Steven Francis (2003) Implementing log-add algorithm in hardware. Electronics Letters, 39 (12). pp. 939-941.
URL of Published Version: http://ieeexplore.ieee.org/iel5/2220/27211/01209507.pdf?isnumber=&arnumber=1209507
Identification Number/DOI: 10.1049/el:20030594
A hardware implementation of the log-add algorithm, being a simple method of computing ln(A + B) given ln(A) and ln(B), as used in speech recognition, is presented. It is shown that it can be efficiently implemented in hardware using a small look-up table plus some additional arithmetic logic, with no significant loss of accuracy over direct calculation.
|Type of Work:||Article|
|Date:||12 June 2003 (Publication)|
|School/Faculty:||Schools (1998 to 2008) > School of Engineering|
|Department:||Electronic, Electrical and Computer Engineering|
This paper is a postprint of a letter submitted to and accepted for publication in Electronics Letters and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at IET Digital Library.
|Subjects:||TK Electrical engineering. Electronics Nuclear engineering|
QA75 Electronic computers. Computer science
|Institution:||University of Birmingham|
|Copyright Holders:||Institution of Engineering and Technology|
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